1. Field of Invention
The present invention relates to a method of manufacturing a shallow trench isolation. More particularly, the present invention relates to a method of preventing current leakage around a shallow trench isolation structure by controlling the ion implantation process.
2. Description of Related Art
A metal-oxide-semiconductor (MOS) typically comprises source/drain regions and a gate on a substrate. To form the source/drain regions and to adjust a threshold voltage of the substrate, pentavalent or trivalent ions are implanted. For example, pentavalent ions are implanted into a P-type substrate to form the source/drain region of an NMOS device. The purpose of doping the substrate with ions is to transform the electrical properties of the wafer. While being accelerated and implanted to a silicon wafer, the ions with an energy collide with silicon atoms of the wafer until the energy of the ions is consumed and released. Typically, ion implantation processes employ ions having an energy level of between 50 to 500 KeV. Hence, the ions are implanted at a position under the substrate surface with a depth between 0.01 .mu.m to 1 .mu.m.
In ion implantation, an ion implanter is used to generate a beam of high-energy ions, which are injected into the substrate. In the fabrication process of semiconductor devices, ion implantation technique has several advantages such as is free from contamination, large area of impurity distribution, performed in a room temperature, precis distribution of concentration. Over the solid solubility, and to dope certain area as required. Hence, ion implantation is widely used in semiconductor fabrication.
However, ion implantation also has its disadvantages. The lattice structure of the substrate is easily destroyed or damaged, so that a high temperature annealing process is required to rearrange the lattice structure. By controlling the temperature and process time, impurities are electrically activated, that is, the carriers regain a mobility under an equilibrium. Thus, the damage of the lattice structure is mended. The temperature and annealing period must be carefully controlled to avoid to converted properties of selected materials. Yet, while ions are implanted with a very large energy, or very heavy ions are implanted, the damage of lattice structure is too serious to mend.
In integrated circuits of VLSI or ULSI, the number of transistors included is huge and the devices are densely packed together. Therefore, in order to prevent any short-circuiting between neighboring transistors, the neighboring transistors have to be isolated by an isolation structure. The most general type of device isolation structure is shallow trench isolation. In the process of forming an NMOS transistor, the source/drain regions are formed by performing an ion implantation. Arsenic (As) ions are implanted into a P-type substrate so that an N-type source/drain region is formed. However, since an arsenic ion has a high atomic weight, serious dislocation of the crystal lattice may occur after the ion implantation. Consequently, leakage current may flow from the device. As line width of semiconductor device falls to below 0.25 .mu.m, isolating devices using a field oxide layer become infeasible. Therefore, shallow trench isolation becomes the only means of device isolation. However, the formation of a shallow trench isolation structure within the substrate tends to retain internal stress. If dopants having a high atomic weight are used in ion implantation, large voids or defects may be generated within the crystal lattice. These voids or defects may not disappear even after a high-temperature annealing treatment inside a furnace. In addition, the annealing temperature and annealing period is further restricted by the demand for minimum device reliability. Ultimately, these crystal defects may lead to the flow of a leakage current from the device.